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Fully-analog in-memory computing (IMC) architectures that implement both matrix-vector multiplication and non-linear vector operations within the same memory array have shown promising performance benefits over conventional IMC systems due…

It is generally impossible to separately measure the resistance of the functional component (i.e., the intrinsic device materials) and the parasitic component (i.e., terminals, interfaces and serial loads) in a two-terminal device. Yet such…

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom…

To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters…

Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper…

In this paper we present a comprehensive design and benchmarking study of Content Addressable Memory (CAM) at the 7nm technology node in the context of similarity search applications. We design CAM cells based on SRAM, spin-orbit torque,…

The crosstalk noise model for noise constrained interconnects optimization is presented for RC interconnects. The proposed model has simple closed-form expressions, which is capable of predicting the noise amplitude and the noise pulse…

The dependency on the correct functioning of embedded systems is rapidly growing, mainly due to their wide range of applications, such as micro-grids, automotive device control, health care, surveillance, mobile devices, and consumer…

This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resistance of the on-chip interconnect in the impact mechanism.…

As the process technologies scale into deep submicron region, crosstalk delay is becoming increasingly severe, especially for global on-chip buses. To cope with this problem, accurate delay models of coupled interconnects are needed. In…

Traditional computing hardware often encounters on-chip memory bottleneck on large scale Convolution Neural Networks (CNN) applications. With its unique in-memory computing feature, resistive crossbar-based computing attracts researchers'…

While in a triggered experiment the matching of the RPC transmission line impedance with the one of the front-end electronics is less critical, for a trigger-less data recording this becomes mandatory. As expected, impedance matching is not…

Interconnected systems such as power systems and chemical processes are often required to satisfy safety properties in the presence of faults and attacks. Verifying safety of these systems, however, is computationally challenging due to…

The number of interconnected devices is growing constantly due to rapid digitalization, thus providing attackers with a larger attack surface. Particularly in critical infrastructures and manufacturing, where processes can be observed and…

We present and evaluate the ExaNeSt Prototype, a liquid-cooled rack prototype consisting of 256 Xilinx ZU9EG MPSoCs, 4 TBytes of DRAM, 16 TBytes of SSD, and configurable interconnection 10-Gbps hardware. We developed this testbed in…

Nanoscale electronics and novel fabrication technologies bear unique opportunities for self-assembling multi-billion component systems in a largely random manner, which would likely lower fabrication costs significantly compared to a…

We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and…

Superconducting circuits with coupler architecture receive considerable attention due to their advantages in tunability and scalability. Although single-qubit gates with low error have been achieved, high-fidelity two-qubit gates in coupler…

With the rapid development of internet Router, the complexity of its mainboard has been growing dramatically. The high reliability requirement renders the number of testing cases increasing exponentially, which becomes the bottleneck that…

Due to the need for higher reliability and performance from RF circuits, multi-port reflectometers are increasingly used as low-overhead impedance monitors. In this work, using periodic structures as multi-ports is proposed. Periodic…