On Irregular Interconnect Fabrics for Self-Assembled Nanoscale Electronics
Abstract
Nanoscale electronics and novel fabrication technologies bear unique opportunities for self-assembling multi-billion component systems in a largely random manner, which would likely lower fabrication costs significantly compared to a definite ad hoc assembly. It has been shown that communication networks with the small-world property have major advantages in terms of transport characteristics and robustness over regularly connected systems. In this paper we pragmatically investigate the properties of an irregular, abstract, yet physically plausible small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, the number of switch blocks, the number of virtual channels, the routing strategy, the distribution of long- and short-range connections, and measure the network's transport characteristics and robustness against failures. We further explore the ability and efficiency to solve two simple toy problems, the synchronization and the density classification task. The results confirm that (1) computation in irregular assemblies is a promising new computing paradigm for nanoscale electronics and (2) that small-world interconnect fabrics have major advantages over local CA-like topologies. Finally, the results will help to make important design decisions for building self-assembled electronics in a largely random manner.
Cite
@article{arxiv.cond-mat/0606584,
title = {On Irregular Interconnect Fabrics for Self-Assembled Nanoscale Electronics},
author = {Christof Teuscher},
journal= {arXiv preprint arXiv:cond-mat/0606584},
year = {2007}
}
Comments
Published at the 2nd IEEE International Workshop on Default and Fault Tolerant Nanoscale Architectures, NANOARCH'06, June 17, 2006, Boston, MA, USA