Related papers: The role of the Fermi level pinning in gate tunabl…
Graphene nanoribbons (GNRs) have been proposed as potential building blocks for field effect transistor (FET) devices due to their quantum confinement bandgap. Here, we propose a novel GNR device concept, enabling the control of both charge…
We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on n-type Si wafer. The original layout, where…
A low complexity computational model of the current-voltage characteristics for graphene nano-ribbon (GNR) field effect transistors (FET), able to simulate a hundred of points in few seconds using a PC, is presented. For quantum capacitance…
The physical origin of Fermi level pinning (FLP) at metal/Ge interfaces has been argued over a long period. Using the Fe$_{3}$Si/Ge(111) heterostructure developed originally, we can explore electrical transport properties through atomically…
At semiconductor-metal junctions, the Schottky barrier height is generally fixed by "Fermi-level pinning". We find that when a semiconducting carbon nanotube is end-contacted to a metal (the optinal geometry for nanodevices), the behavior…
The problem of Fermi-level pinning at semiconductor-metal contacts is readdressed starting from first-principles calculations for Al/GaAs. We give quantitative evidence that the Schottky barrier height is very little affected by any…
A systematic treatment of graphene-semiconductor junction is presented. Finite density of states at the Fermi level of graphene leads to exotic electronic properties at graphene-semiconductor interface. Quite generally, the Schottky-Mott…
We propose encapsulating type-A antiferromagnetic semiconductors between graphene layers to realize a gate-tunable synthetic antiferromagnet with nonrelativistic spin splitting, enabling efficient spintronic transport via graphene. Ab…
Strong Fermi level pinning (FLP) - often attributed to metal-induced gap states at the interfacial contacts - severely reduces the tunability of the Schottky barrier height of the junction and limits applications of the 2D materials in…
We fabricate a vertical thin-film barristor device consisting of highly doped silicon (gate), 300 nm SiO2 (gate dielectric), monolayer graphene, pentacene, and a gold top electrode. We show that the current across the device is modulated by…
A graphene field effect transistor, where the active area is made of monolayer large-area graphene, is simulated including a full 2D Poisson equation and a drift-diffusion model with mobilities deduced by a direct numerical solution of the…
Schottky barrier field-effect transistors (SBFETs) based on few and mono layer phosphorene are simulated by the non-equilibrium Green's function formalism. It is shown that scaling down the gate oxide thickness results in pronounced…
The superior intrinsic properties of graphene have been a key research focus for the past few years. However, external components, such as metallic contacts, serve not only as essential probing elements, but also give rise to an effective…
It is demonstrated that the electric dipole layer due to the overlapping of electron wavefunctions at metal/graphene contact results in negative Fermi-level pinning effect on the region of GaAs surface with low interface-trap density in…
The topological quantum field-effect transition in buckled 2D-Xenes can potentially be engineered to enable sub-thermionic transistor operation coupled with dissipationless ON-state conduction. Substantive device design strategies to…
Graphene/silicon heterostructures have attracted tremendous interest as a new platform for diverse electronic and photonic devices such as barristors, solar cells, optical modulators, and chemical sensors. The studies to date largely focus…
The paradigm of graphene transistors is based on the gate modulation of the channel carrier density by means of a local channel gate. This standard architecture is subject to the scaling limit of the channel length and further restrictions…
By using four layered graphene/gallium nitride (GaN) Schottky diodes with an undoped GaN spacer, we demonstrate highly effective gating of graphene at low bias rendering this type of structure very promising for potential applications. An…
We present electronic structure calculations of few-layer epitaxial graphene nanoribbons on SiC(0001). Trough an atomistic description of the graphene layers and the substrate within the extended H\"{u}ckel Theory and real/momentum space…
This paper reviews the current status of graphene transistors as potential supplement to silicon CMOS technology. A short overview of graphene manufacturing and metrology methods is followed by an introduction of macroscopic graphene field…