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Ion trap technologies have earned significant attention as potential candidates for quantum information processing due to their long decoherence times and precise manipulation of individual qubits, distinguishing them from other candidates…
Multimodal Transformers are emerging artificial intelligence (AI) models designed to process a mixture of signals from diverse modalities. Digital computing-in-memory (CIM) architectures are considered promising for achieving high…
The long-term average performance of the MISO downlink channel, with a large number of users compared to transmit antennas of the BS, depends on the interference management which necessitates the joint design problem of scheduling and…
Currently, the superconducting diode effect (SDE) is actively discussed due to large application potential in superconducting electronics. In particular, the superconducting hybrid structures based on three-dimensional (3D) topological…
The design of coupler-based superconducting two-qubit gates simplifies circuit layout and alleviate frequency crowding, thereby enhancing the scalability and flexibility of quantum chips. However, in such architectures, a trade-off often…
Reduction multigrids have recently shown good performance in hyperbolic problems without the need for Gauss-Seidel smoothers. When applied to the hyperbolic limit of the Boltzmann Transport Equation (BTE), these methods result in very close…
Besides striving to assemble more and more qubits in a single monolithic quantum device, taking a modular design strategy may mitigate numerous engineering challenges for achieving large-scalable quantum processors with superconducting…
In this work, using 3D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the on-off…
Tiled spatial architectures have proved to be an effective solution to build large-scale DNN accelerators. In particular, interconnections between tiles are critical for high performance in these tile-based architectures. In this work, we…
The potential of a wide range of layered ternary carbide and nitride MAX phases as conductors in interconnect metal lines in advanced CMOS technology nodes has been evaluated using automated first principles simulations based on density…
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between layers and significantly alleviating main memory bottlenecks.…
The level-set method of topology optimization is used to design isotropic two-phase periodic multifunctional composites in three dimensions. One phase is stiff and insulating whereas the other is conductive and mechanically compliant. The…
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect…
The Mixture-of-Experts (MoE) models have emerged as the state-of-the-art paradigm for scaling up large language models (LLMs) without proportionally increased computational cost. However, its on-device deployment faces a critical challenge…
Reconfigurable intelligent surface (RIS) is a promising technology for future wireless communication systems. Conventional RIS is constrained to a diagonal scattering matrix, which limits its flexibility. Recently, beyond-diagonal RIS…
Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum…
Beyond-diagonal reconfigurable intelligent surface (BD-RIS) has garnered significant research interest recently due to its ability to generalize existing reconfigurable intelligent surface (RIS) architectures and provide enhanced…
Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry. Prior work has shown that this shortcoming can be overcome by reducing the critical length of DRAM access…
Two-dimensional (2D) semiconductors have been suggested both for ultimately-scaled field-effect transistors (FETs) and More-than-Moore nanoelectronics. However, these targets can not be reached without accompanying gate insulators which are…
Topological insulators (TIs) have the singular distinction of being electronic insulators while harboring metallic, conductive surfaces. In ordinary materials, defects such as cracks and deformations are barriers to electrical conduction,…