Related papers: A Prototype Scalable Readout System for Micro-patt…
PARISROC is a complete read out chip, in AMS SiGe 0.35 !m technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national…
A segmented waveguide-enabled pinching-antenna system (SWAN)-assisted integrated sensing and communications (ISAC) framework is proposed. Unlike conventional pinching antenna systems (PASS), which use a single long waveguide, SWAN divides…
Short circuit ratio (SCR) is widely applied to analyze the strength of AC system and the small signal stability for single power elec-tronic based devices infeed systems (SPEISs). However, there still lacking the theory of short circuit…
This chapter focuses on a hardware architecture for semi-passive Reconfigurable Intelligent Surfaces (RISs) and investigates its consideration for boosting the performance of Multiple-Input Multiple-Output (MIMO) communication systems. The…
Frequency-selective readout for superconducting qubits opens the way towards scaling qubit circuits up without increasing the number of measurement lines. Here we demonstrate the readout of an array of 7 flux qubits located on the same…
This paper presents a 1-bit reconfigurable intelligent surface (RIS) fabricated using a three-layer structure. It employs a manual layer stackup incorporating an optimal air gap to reduce the effective dielectric losses while using a…
The STS-MUCH-XYTER (SMX) chip is a front-end ASIC dedicated to the readout of Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the Compressed Baryonic Matter (CBM) experiment. The production of the ASIC and the front-end…
Resistive AC-coupled Silicon Detectors (RSDs) are based on the Low Gain Avalanche Diode (LGAD) technology, characterized by a continuous gain layer, and by the innovative introduction of resistive read-out. Thanks to a novel electrode…
In this paper, we investigate a bistatic multiple-input multiple-output (MIMO) integrated sensing and communication (ISAC) system over block-fading channels, focusing on the scenario where the sensing and communication receivers (Rxs) are…
A front end ASIC (BiCMOS-SiGe 0.35 \mum) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy…
In this letter, we describe operation of a radio-frequency superconducting single electron transistor (RF-SSET) with an on-chip superconducting LC matching network consisting of a spiral inductor L and its capacitance to ground. The…
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform…
This paper presents CARTS, an adaptive 5G uplink sensing scheme designed to provide Integrated Sensing and Communication (ISAC) services. The performance of both communication and sensing fundamentally depends on the availability of…
Spatially-coupled (SC) codes are a class of low-density parity-check (LDPC) codes that have excellent performance thanks to the degrees of freedom they offer. An SC code is designed by partitioning a base matrix into components, the number…
This paper presents a novel framework for enhancing physical-layer security in integrated sensing and communication (ISAC) systems by leveraging the reconfigurability of fluid antenna systems (FAS). We propose a joint precoding and port…
Large Resistive Plate Chamber systems have their roots in High Energy Physics experiments at the European Organization for Nuclear Research: ATLAS, CMS and ALICE, where hundreds of square meters of both trigger and timing RPCs have been…
We report on progress in the development of the LSTFE2 prototype front-end ASIC geared towards the readout of silicon microstrip sensors in a Linear Collider detector. We also discuss progress in the design of the back-end digital…
A prototype flash analog-to-digital readout system for cosmic ray detection at energies below 10^18 eV has been designed and tested at Columbia University Nevis Laboratories. The electronics consist of an FADC module that digitizes 16…
The Pad Front End Board (pFEB) and the Strip Front End Board (sFEB) are developed for the ATLAS Phase-I sTGC Trigger Upgrade. The pFEB is used to to gather and analyze pads trigger, and the sFEB is developed to accept the pad trigger to…
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $\mu$-TPCs for directional dark matter searches. Low-noise…