Related papers: FPGA based Novel High Speed DAQ System Design with…

Deep neural network (DNN) inference relies increasingly on specialized hardware for high computational efficiency. This work introduces a field-programmable gate array (FPGA)-based dynamically configurable accelerator featuring systolic…

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of…

Synthetic Aperture Radar (SAR) plays a vital role in remote sensing due to its ability to capture high-resolution images regardless of weather conditions or daylight. However, to transform the raw SAR signals into interpretable imagery,…

We develop a custom Bit Error Rate test bench based on Altera's Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial…

Multi-qubit parity measurements are at the core of many quantum error correction schemes. Extracting multi-qubit parity information typically involves using a sequence of multiple two-qubit gates. In this paper, we propose a superconducting…

To satisfy the growing throughput demand of data-intensive applications, the performance of optical communication systems increased dramatically in recent years. With higher throughput, more advanced equalizers are crucial, to compensate…

Blind quantum computing (BQC) is a computational paradigm that allows a client with limited quantum capabilities to delegate quantum computations to a more powerful server while keeping both the algorithm and data hidden. However, in…

Caribou is a versatile data acquisition (DAQ) system developed within several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, and Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It…

Field Programmable Gate Array (FPGA) is widely used in acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the tradeoff between chip area…

Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the…

Deep learning-based image compression (LIC) has achieved state-of-the-art rate-distortion (RD) performance, yet deploying these models on resource-constrained FPGAs remains a major challenge. This work presents a complete, multi-stage…

Model quantization is a widely used technique to compress and accelerate deep neural network (DNN) inference. Emergent DNN hardware accelerators begin to support mixed precision (1-8 bits) to further improve the computation efficiency,…

We have built a high precision (24-bit) data acquisition (DAQ) system with eight simultaneously sampling input channels for the measurement of the electric dipole moment (EDM) of the electron. The DAQ system consists of two main components,…

Effects of radiation on electronic circuits used in extra-terrestrial applications and radiation prone environments need to be corrected. Since FPGAs offer flexibility, the effects of radiation on them need to be studied and robust methods…

Time-tagging units and coincidence detectors are used in many scientific research fields. The required timing resolution and number of input channels are varying, but some emerging experiments in the field of quantum optics require up to 32…

The noisy nature of quantum hardware necessitates the implementation of high-fidelity quantum gates in a noise-insensitive manner. While there exist many powerful methods for designing dynamically corrected gates, they typically involve an…

Noise and errors are inevitable parts of any practical implementation of a quantum computer. As a result, large-scale quantum computation will require ways to detect and correct errors on quantum information. Here, we present such a quantum…

A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated…

A variety of computing platform like Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in data centers are suitable for acceleration of data-intensive workloads. Especially,…

Forget and Rewire (FaR) methodology has demonstrated strong resilience against Bit-Flip Attacks (BFAs) on Transformer-based models by obfuscating critical parameters through dynamic rewiring of linear layers. However, the application of FaR…