Related papers: FPGA Based Data Read-Out System of the Belle 2 Pix…

Digital off-detector electronics in trigger and data acquisition systems of High-Energy Physics experiments is often implemented by means of SRAM-based FPGAs, which make it possible to achieve reconfigurable, real-time processing and…

The high-luminosity upgrade of the CERN LHC requires the replacement of the CMS tracking detector to cope with the increased radiation fluence while maintaining its excellent performance. An extensive R\&D program, aiming at using 3D pixel…

A significant upgrade of the LHCb detector is scheduled to be installed in 2018-2019. Afterwards all sub-detectors will be read out at the LHC bunch crossing frequency of 40 MHz and the trigger will be fully implemented in software. The…

To cope with the High Luminosity LHC harsh conditions, the ATLAS inner tracker has to be upgraded to meet requirements in terms of radiation hardness, pile up and geometrical acceptance. The active edge technology allows to reduce the…

In high energy physics experiments (HEP), high speed and fault resilient data communication is needed between detectors/sensors and the host PC. Transient faults can occur in the communication hardware due to various external effects like…

Image feature extraction and matching is a fundamental but computation intensive task in machine vision. This paper proposes a novel FPGA-based embedded system to accelerate feature extraction and matching. It implements SURF feature point…

In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA)…

This paper describes a step by step approach for implementing a scalable and run-time adaptable multi-standard packet detector for orthogonal frequency divisional multiplexing (OFDM) based communication standards. The paper briefly…

The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a dual-precision…

The next upgrade of the Large Hadron Collider (LHC) is planned from 2026 when the collider will move to its High Luminosity phase (HL-LHC). The CMS detector needs to be substantially upgraded during this period to exploit the fourfold…

At least 25 kinds of detector-like devices need to be integrated in Phase I of the High Energy Photon Source (HEPS), and the work needs to be carefully planned to maximise productivity with highly limited human resources. After a systematic…

The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key…

We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ (Quad Small Form Pluggable +) module. QSFP+ standard defines a hot-pluggable transceiver available in copper…

We describe a neural network for predicting the background hit rate in the Belle II detector produced by the SuperKEKB electron-positron collider. The neural network, BGNet, learns to predict the individual contributions of different…

The Belle II experiment aims to record 50 ab$^{-1}$ data with the high luminosity to be provided by the SuperKEKB asymmetric-energy electron-positron collider. The anticipated high statistics data enables us to perform studies of $B$ decays…

The Large Hadron Collider (LHC) at CERN will undergo an upgrade in order to increase its luminosity to $7.5 \times 10^{34}$ cm$^{-2}$s$^{-1}$. The increased luminosity during this High-Luminosity running phase (HL-LHC), starting around…

A new FPGA-based low-level trigger processor has been installed at the NA62 experiment. It is intended to extend the features of its predecessor due to a faster interconnection technology and additional logic resources available on the new…

Obtaining highly accurate depth from stereo images in real time has many applications across computer vision and robotics, but in some contexts, upper bounds on power consumption constrain the feasible hardware to embedded platforms such as…

High backgrounds and detector ageing impact the track finding in the Belle II central drift chamber, reducing both track purity and track efficiency in events. This necessitates the development of new track finding algorithms to mitigate…

When trained as generative models, Deep Learning algorithms have shown exceptional performance on tasks involving high dimensional data such as image denoising and super-resolution. In an increasingly connected world dominated by mobile and…