Related papers: FPGA Based Data Read-Out System of the Belle 2 Pix…
With the increasing physical event rate and number of electronic channels, traditional readout scheme meets the challenge of improving readout speed caused by the limited bandwidth of crate backplane. In this paper, a high-speed data…
We introduce a prototype FPGA decoder implementing the recently discovered Relay-BP algorithm and targeting memory experiments on the $[[144,12,12]]$ bivariate bicycle quantum low-density parity check code. The decoder is both fast and…
Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC…
The BeEST experiment is a precision laboratory search for physics beyond the standard model that measures the electron capture decay of $^7$Be implanted into superconducting tunnel junction (STJ) detectors. For Phase-III of the experiment,…
The Belle II experiment, which is situated at the interaction point of the SuperKEKB $e^+e^{-}$ collider at KEK, Tsukuba, Japan, is expected to collect data corresponding to an integrated luminosity of 50~ab$^{- 1}$. This data set will be…
In this paper, we implement a stand-alone facial expression recognition system on an SoC FPGA with multi-threading using a Deep learning Processor Unit (DPU). The system consists of two steps: one for face detection step and one for facial…
The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the…
The ATLAS experiment pixel detector upgrade plans are focused on development of new technology, including the FE-I4 readout integrated circuit. The first upgrade project to make use of this new technology is an "Insertable B-Layer" (IBL)…
A new pixel detector for the CMS experiment was built in order to cope with the instantaneous luminosities anticipated for the Phase~I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking with a reduced material budget…
Since the start of data taking in spring 2019 at the SuperKEKB collider (KEK, Japan) the Belle II Silicon Vertex Detector (SVD) has been operating reliably and with high efficiency, while providing high quality data: high signal-to-noise…
Accelerating Human Action Recognition (HAR) efficiently for real-time surveillance and robotic systems on edge chips remains a challenging research field, given its high computational and memory requirements. This paper proposed an…
BDAQ53 is a readout system and verification framework for hybrid pixel detector readout chips of the RD53 family. These chips are designed for the upgrade of the inner tracking detectors of the ATLAS and CMS experiments. BDAQ53 is used in…
The Belle detector operated at KEKb B-factory in 1999-2010 was one of the most remarkable experiments in the field of elementary particle physics of the last decades. The Belle successor, Belle II collaboration, is aimed to operate the…
A new type of ring-imaging Cherenkov counter, called TOP counter, has been developed for particle identification at the Belle II experiment to run at the SuperKEKB accelerator in KEK, Japan. The detector consists of 16 identical modules…
The Belle II experiment's ability to identify particles critically affects the sensitivity of its measurements. We describe Belle II's algorithms for identifying charged particles and evaluate their performance in separating pions, kaons,…
The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and…
This research introduces an FPGA-based hardware accelerator to optimize the Singular Value Decomposition (SVD) and Fast Fourier transform (FFT) operations in AI models. The proposed design aims to improve processing speed and reduce…
The RD50-CMOS group aims to design and study High Voltage CMOS (HVCMOS) chips for use in a high radiation environment. Currently, measurements are performed on RD50-MPW2 chip, the second prototype developed by this group. The active matrix…
A new tracking detector will be installed as part of the Phase-2 upgrade of the CMS detector for the high-luminosity LHC era. This tracking detector includes the Inner Tracker, equipped with silicon pixel sensor modules, and the Outer…
With the growing demand of real-time traffic monitoring nowadays, software-based image processing can hardly meet the real-time data processing requirement due to the serial data processing nature. In this paper, the implementation of a…