Related papers: Dual Metal-Gate Planar Field-Effect Transistor for…
We demonstrate dual-gated $p$-type field-effect transistors (FETs) based on few-layer tungsten diselenide (WSe$_2$) using high work-function platinum source/drain contacts, and a hexagonal boron nitride top-gate dielectric. A device…
Thickness engineered tunneling field-effect transistors (TE-TFET) as a high performance ultra-scaled steep transistor is proposed. This device exploits a specific property of 2D materials: layer thickness dependent energy bandgap (Eg).…
We present the study of using depletion charges for tailoring lateral band profiles and applying it to the promising gate-all-around field-effect transistors (GAAFET). Specifically, we introduce heavily p-type doped Si next to the channel,…
An analytical expression is derived for the conductance modulation of a ballistic two dimensional Datta-Das Spin Field Effect Transistor (SPINFET) as a function of gate voltage. Using this expression, we show that the recently observed…
Two-dimensional (2D) semiconductors are likely to dominate next-generation electronics due to their advantages in compactness and low power consumption. However, challenges such as high contact resistance and inefficient doping hinder their…
Vertical field effect transistors (VFETs) show many advantages such as high switching speed, low operating voltage, low power consumption, and miniaturization over lateral FETs. However, VFET still faces the main challenges of high…
We investigate transport through ionic liquid gated field effect transistors (FETs) based on exfoliated crystals of semiconducting WS$_2$. Upon electron accumulation, at surface densities close to -or just larger than- 10$^{14}$ cm$^{-2}$,…
Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit…
Excellent gate electrostatics in field effect transistors (FETs) based on two-dimensional transition metal dichalcogenide (2D TMD) channels can dramatically decrease static power dissipation. Energy efficient FETs operate in enhancement…
With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high Off currents except at low drain voltages. We show that an asymmetric design improves the performance, reducing Off…
A nanoscale device consisting of a metal nanowire, a dielectric, and a gate is proposed. A combination of quantum and thermal stochastic effects enable the device to have multiple functionalities, serving alternately as a transistor, a…
An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for…
We propose and numerically simulate novel reconfigurable logic gates employing spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The output characteristics of the spin MOSFETs depend on the relative magnetization…
Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized…
A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that…
Inducing an inversion layer in organic semiconductors is a highly nontrivial, but critical, achievement for producing organic field-effect transistor (OFET) devices, which rely on the generation of inversion, accumulation, and depletion…
Schottky barrier field-effect transistors (SBFETs) based on few and mono layer phosphorene are simulated by the non-equilibrium Green's function formalism. It is shown that scaling down the gate oxide thickness results in pronounced…
Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally-decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal…
In this work, we report on the electronic properties of solution-gated field effect transistors (SGFETs) fabricated using large-area graphene. Devices prepared both with epitaxially grown graphene on SiC as well as with chemical vapor…
Ten years have passed since the beginning of graphene research. In this period we have witnessed breakthroughs both in fundamental and applied research. However, the development of graphene devices for mass production has not yet reached…