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Related papers: Rank-Modulation Rewrite Coding for Flash Memories

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This paper investigates the design and application of write-once memory (WOM) codes for flash memory storage. Using ideas from Merkx ('84), we present a construction of WOM codes based on finite Euclidean geometries over $\mathbb{F}_2$.…

Information Theory · Computer Science 2012-06-26 Kathryn Haymaker , Christine A. Kelley

The pivotal storage density win achieved by solid-state devices over magnetic devices in 2015 is a result of multiple innovations in physics, architecture, and signal processing. One of the most important innovations in that regard is…

Information Theory · Computer Science 2022-09-07 Ahmed Hareedy , Simeng Zheng , Paul Siegel , Robert Calderbank

The pivotal storage density win achieved by solid-state devices over magnetic devices recently is a result of multiple innovations in physics, architecture, and signal processing. Constrained coding is used in Flash devices to increase…

Information Theory · Computer Science 2023-11-15 Ahmed Hareedy , Simeng Zheng , Paul Siegel , Robert Calderbank

The read channel of a Flash memory cell degrades after repetitive program and erase (P/E) operations. This degradation is often modeled as a function of the number of P/E cycles. In contrast, this paper models the degradation as a function…

Information Theory · Computer Science 2016-10-13 Haobo Wang , Nathan Wong , Tsung-Yi Chen , Richard D. Wesel

In this paper, we consider modulation codes for practical multilevel flash memory storage systems with cell levels. Instead of maximizing the lifetime of the device [Ajiang-isit07-01, Ajiang-isit07-02, Yaakobi_verdy_siegel_wolf_allerton08,…

Information Theory · Computer Science 2009-10-13 Fan Zhang , Henry D. Pfister

Local rank modulation scheme was suggested recently for representing information in flash memories in order to overcome drawbacks of rank modulation. For $0 < s\leq t\leq n$ with $s$ divides $n$, an $(s,t,n)$-LRM scheme is a local rank…

Information Theory · Computer Science 2014-04-22 Michal Horovitz , Tuvi Etzion

Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high-performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Among candidate solid-state…

Hardware Architecture · Computer Science 2017-04-19 Wonil Choi , Mohammad Arjomand , Myoungsoo Jung , Mahmut Kandemir

Raw bit errors are common in NAND flash memory and will increase in the future. These errors reduce flash reliability and limit the lifetime of a flash memory device. We aim to improve flash reliability with a multitude of low-cost…

Hardware Architecture · Computer Science 2018-08-16 Yixin Luo

Due to increasing cache sizes and large leakage consumption of SRAM device, conventional SRAM caches contribute significantly to the processor power consumption. Recently researchers have used non-volatile memory devices to design caches,…

Hardware Architecture · Computer Science 2014-05-01 Sparsh Mittal

Flash memory is a non-volatile computer memory comprised of blocks of cells, wherein each cell can take on q different levels corresponding to the number of electrons it contains. Increasing the cell level is easy; however, reducing a cell…

Information Theory · Computer Science 2015-03-13 Eitan Yaakobi , Alexander Vardy , Paul H. Siegel , Jack K. Wolf

A rewriting code construction for flash memories based upon lattices is described. The values stored in flash cells correspond to lattice points. This construction encodes information to lattice points in such a way that data can be written…

Information Theory · Computer Science 2010-07-13 Brian M. Kurkoski

The aggressive scaling down of flash memories has threatened data reliability since the scaling down of cell sizes gives rise to more serious degradation mechanisms such as cell-to-cell interference and lateral charge spreading. The effect…

Information Theory · Computer Science 2014-12-11 Yongjune Kim , Kyoung Lae Cho , Hongrak Son , Jaehong Kim , Jun Jin Kong , Jaejin Lee , B. V. K. Vijaya Kumar

To mitigate the impact of noise and interference on multi-level-cell (MLC) flash memory with the use of low-density parity-check (LDPC) codes, we propose a dynamic write-voltage design scheme considering the asymmetric property of raw bit…

Signal Processing · Electrical Eng. & Systems 2022-09-07 Runbin Cai , Yi Fang , Zhifang Shi , Lin Dai , Guojun Han

Rank modulation is a way of encoding information to correct errors in flash memory devices as well as impulse noise in transmission lines. Modeling rank modulation involves construction of packings of the space of permutations equipped with…

Information Theory · Computer Science 2011-10-13 Arya Mazumdar , Alexander Barg , Gilles Zémor

Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory failures are 1) wear-leveling, to evenly distribute the writes…

Hardware Architecture · Computer Science 2020-10-07 Leonid Yavits , Lois Orosa , Suyash Mahar , João Dinis Ferreira , Mattan Erez , Ran Ginosar , Onur Mutlu

Codes for rank modulation have been recently proposed as a means of protecting flash memory devices from errors. We study basic coding theoretic problems for such codes, representing them as subsets of the set of permutations of $n$…

Information Theory · Computer Science 2010-12-10 Alexander Barg , Arya Mazumdar

Flash-based disk caches, for example Bcache and Flashcache, has gained tremendous popularity in industry in the last decade because of its low energy consumption, non-volatile nature and high I/O speed. But these cache systems have a worse…

Operating Systems · Computer Science 2023-11-16 Chaos Dong , Fang Wang , Jianshun Zhang

Large language models (LLMs) are central to modern natural language processing, delivering exceptional performance in various tasks. However, their substantial computational and memory requirements present challenges, especially for devices…

Lengthening a computer memory's lifespan is important for e-waste and sustainability. Uneven wear of memory is a major barrier. The problem is becoming even more urgent as emerging memory such as phase-change memory is subject to even…

Hardware Architecture · Computer Science 2026-01-29 Elizabeth Shen , Huiyang Zhou

This paper summarizes our work on experimentally characterizing, mitigating, and recovering data retention errors in multi-level cell (MLC) NAND flash memory, which was published in HPCA 2015, and examines the work's significance and future…

Hardware Architecture · Computer Science 2018-05-09 Yu Cai , Yixin Luo , Erich F. Haratsch , Ken Mai , Saugata Ghose , Onur Mutlu