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This paper proposes a Low-Power, Energy Efficient 4-bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth)…

In many modern AI chips and multicore systems-on-chip, embedded applications exhibit predictable inter-core traffic behavior that can be characterized at design time. For such applications, a variety of design-time traffic management and…

Computer vision performances have been significantly improved in recent years by Convolutional Neural Networks(CNN). Currently, applications using CNN algorithms are deployed mainly on general purpose hardwares, such as CPUs, GPUs or FPGAs.…

Sensor nodes and IoT systems require blocks that not only consume low power but also have good accuracy. Voltage reference generators are also considered important building blocks in sensor interface circuits. This paper presents a solution…

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate…

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold(NT) operation can…

In this paper, a two-stage ultra-low-power operational amplifier is designed, and a comparative analysis of the proposed subthreshold complementary amplifier is presented between 180nm, 90nm, and 45nm CMOS technology. The proposed…

This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM…

Twisted String Actuators (TSAs) are widely used in robotics but suffer from a limited range of Transmission Ratio (TR) variation, restricting their efficiency under varying loads.To overcome this, we propose a novel lightweight,…

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware…

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the…

This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion…

Object trackers deployed on low-power devices need to be light-weight, however, most of the current state-of-the-art (SOTA) methods rely on using compute-heavy backbones built using CNNs or transformers. Large sizes of such models do not…

In power systems, the distribution network is pivotal for consumers because it is the final stage in the delivery of electricity from the generation plants to the end users. Reactive power demand from consumers can result in challenges like…

The study considers a three-node, two-way relaying network (TWRN) over a multi-carrier system, aiming to minimize the total power consumption of all the transmit and receiver activities. By employing digital network coding (DNC) and…

A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of…

In this paper, we take a fresh look at the physics and operation of Negative Capacitance FETs, and provide unambiguous feedback to the device designers by examining NC-FETs' design space for sub-60 mV/dec Subthreshold Swing (SS).…

Our goal in this paper is to understand how to maximize energy efficiency when designing standard-ISA processor cores for subthreshold operation. We hence develop a custom subthreshold library and use it to synthesize the open-source RISC-V…

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also,…

We consider a variety of NP-Complete network connectivity problems. We introduce a novel dual-based approach to approximating network design problems with cut-based linear programming relaxations. This approach gives a $3/2$-approximation…