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The achievable gains via power-optimal scheduling are investigated. Under the QoS constraint of a guaranteed link rate, the overall power consumed by a cellular BS is minimized. Available alternatives for the minimization of transmit power…

While Cram\'er-Rao lower bound is an important metric in sensing functions in integrated sensing and communications (ISAC) designs, its optimization usually involves a computationally expensive solution such as semidefinite relaxation. In…

The increasing computational demand of Convolutional Neural Networks (CNNs) necessitates energy-efficient acceleration strategies. Compute-in-Memory (CIM) architectures based on Resistive Random Access Memory (RRAM) offer a promising…

This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer…

Machine-type communications (MTC) devices in 5G will use the Non-orthogonal multiple access (NOMA) technology for massive connections. These devices switch between the transmission mode and the sleep mode for battery saving; and their…

Systolic Array (SA) architectures are well suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local connections and pre-orchestrated data movements. Even…

Control Co-Design (CCD) considers the coupled effects of both the plant and control parameters to optimize a system's closed-loop transient performance during the design stage. This paper presents a new method for CCD with guarantees on…

We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO)…

The main areas of research in VLSI system design include area, high speed, and power-efficient data route logic systems. The amount of time needed to send a carry through the adder limits the pace at which addition can occur in digital…

This study focuses on optimizing the design parameters of a Dual Active Bridge (DAB) converter for use in 350 kW DC fast chargers, emphasizing the balance between efficiency and cost. Addressing the observed gaps in existing high-power…

Connected and automated vehicles (CAVs) provide the most intriguing opportunity to reduce energy consumption and travel delays. In this paper, we propose a two-level control architecture for CAVs to optimize (1) the vehicle's speed profile,…

In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided…

This paper presents a fully integrated second-order level-crossing sampling data converter for real-time data compression and feature extraction. Compared with level-sampling ADCs which sample at fixed voltage levels, the proposed circuits…

This technical note compares the performance of some synchronous adders which correspond to the following architectures: i) ripple carry adder (RCA), ii) recursive carry lookahead adder (RCLA), iii) hybrid RCLA-RCA with the RCA used in the…

Carbon nanotube field-effect transistors (CNFET) emerge as a promising alternative to CMOS transistors for the much higher speed and energy efficiency, which makes the technology particularly suitable for building the energy-hungry last…

This paper presents a PVT-resilient, subthreshold SRAM-based computing-in-memory (CIM) macro tailored for energy-efficient spiking neural networks (SNNs). The macro integrates in-situ current sensors and distributed voltage regulators to…

High speed downlink packet access (HSDPA) has been successfully applied in commercial systems and improves user experience significantly. However, it incurs substantial energy consumption. In this paper, we address this issue by proposing a…

State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is…

A four-stage operational transconductance amplifier (OTA) for ultra-low-power applications is introduced in this paper. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the…

Control data separation architecture (CDSA) is a more efficient architecture to overcome the overhead issue than the conventional cellular networks, especially for the huge bursty traffic like Internet of Things, and over-the-top (OTT)…