Related papers: A Low-Voltage, Low-Power 4-bit BCD Adder, designed…
We present the characterization of the CCD system developed for the ADFOSC instrument on the 3.6m Devasthal Optical Telescope (DOT). We describe various experiments performed to tune the CCD controller parameters to obtain optimum…
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…
We propose a new method to measure the system noise temperature, $T_{\rm sys}$, using a 2-bit analog-to-digital converter (ADC). The statistics of the digitized signal in a four-level quantization brings us information about the bias…
This paper proposes a "quasi-synchronous" design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. The case of a low-density parity-check (LDPC)…
The discrete Fourier transform (DFT) is widely employed for multi-beam digital beamforming. The DFT can be efficiently implemented through the use of fast Fourier transform (FFT) algorithms, thus reducing chip area, power consumption,…
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy…
Power consumption has become a critical concern in both high performance and portable applications. Methods for power reduction based on the application of adiabatic techniques to CMOS circuits have recently come under renewed…
This paper presents the design and testing of a time-stretching-based time-to-digital converter (TDC) implemented with discrete components. The TDC utilizes capacitor charging and discharging to achieve a time resolution of under 100 ps…
The goal of this work is to minimize the energy dissipation of embedded controllers without jeopardizing the quality of control (QoC). Taking advantage of the dynamic voltage scaling (DVS) technology, this paper develops a performance-aware…
Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices. For instance, FPGAs can efficiently implement arbitrary-precision arithmetic operations, and can perform…
- This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage…
This paper proposes a novel low complexity joint bit and power suboptimal allocation algorithm for multicarrier systems operating in fading environments. The algorithm jointly maximizes the throughput and minimizes the transmitted power,…
The objective of this paper is to minimize the energy consumption of a quantized Min-Sum LDPC decoder, by considering aggressive voltage downscaling of the decoder circuit. Since low power supply may introduce faults in the memories used by…
One of the major challenges in Wireless Body Area Networks (WBANs) is to prolong the lifetime of network. Traditional research work focuses on minimizing transmit power; however, in the case of short range communication the consumption…
The wideband regime of bit-interleaved coded modulation (BICM) in Gaussian channels is studied. The Taylor expansion of the coded modulation capacity for generic signal constellations at low signal-to-noise ratio (SNR) is derived and used…
Advanced microgrids consisting of distributed energy resources interfaced with multi-inverter systems are becoming more common. Consequently, the effectiveness of voltage and frequency regulation in microgrids using conventional droop-based…
We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the…
A fundamental challenge in quantum computing is to increase the number of operations within the qubit coherence time. While this can be achieved by decreasing the gate duration, the use of shorter signals increases their bandwidth and can…
A current-mode CMOS design is proposed for realizing receive mode multi-beams in the analog domain using a novel DFT approximation. High-bandwidth CMOS RF transistors are employed in low-voltage current mirrors to achieve bandwidths…
Voltage control devices are employed in power distribution systems to reduce the power consumption by operating the system closer to the lower acceptable voltage limits; this technique is called conservation voltage reduction (CVR). The…