Related papers: Low Power Dual Edge-Triggered Static D Flip-Flop

This paper projects the enhanced drive current of a n-type electrostatically doped (ED) tunnel field-effect transistor (ED-TFET) based on heterojunction and band-gap engineering via TCAD 2-D device simulations. The homojunction ED-TFET…

The recent proposed orthogonal time frequency space (OTFS) modulation shows signifcant advantages than conventional orthogonal frequency division multiplexing (OFDM) for high mobility wireless communications. However, a challenging problem…

By interconnecting smaller chiplets through an interposer, 2.5D integration offers a cost-effective and high-yield solution to implement large-scale modular systems. Nevertheless, the underlying network is prone to deadlock, despite…

Background: Windowed Fourier decompositions (WFD) are widely used in measuring stationary and non-stationary spectral phenomena and in describing pairwise relationships among multiple signals. Although a variety of WFDs see frequent…

As energy efficiency became a critical factor in the embedded systems domain, dynamic voltage and frequency scaling (DVFS) techniques have emerged as means to control the system's power and energy efficiency. Additionally, due to the…

Integrated data and energy transfer (IDET) is an advanced technology for enabling energy sustainability for massively deployed low-power electronic consumption components. However, the existing work of IDET using the…

Density functional theory (DFT) can run into serious difficulties with localized states in elements such as transition metals with occupied-d states and oxygen. In contrast, Hartree-Fock (HF) method can be a better approach for such…

Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit…

In current generation digital phase locked loop (DPLL) architectures, techniques like adaptive loop bandwidth with loop order switching and switched phase-detection are employed to achieve better lock time and jitter performance. This work…

Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps…

An array of DEPFET pixels is one of several concepts to implement an active pixel sensor. Similar to PNCCD and SDD detectors, the typically 0.45 mm thick silicon sensor is fully depleted by the principle of sideward depletion. They have…

In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on…

The cold source field-effect transistor (CSFET) is promising for reducing power dissipation in integrated circuits by engineering the density of states at the injecting source. Existing CSFET designs utilizing Dirac-source metals or…

Rapid single-flux quantum (RSFQ), a leading cryogenic superconductive electronics (SCE) technology, offers extremely low power dissipation and high speed. However, implementing RSFQ systems at VLSI complexity faces challenges, such as…

Dual-material double-gate tunnel field effect transistor (DMDG TFET) is a promising candidate for low-power, high-speed electronics due to enhanced electrostatic control and superior switching characteristics. Integrating a pocket region…

In this paper, a new single-carrier waveform, called chirped discrete Fourier transform spread orthogonal frequency division multiplexing (DFT-s-OFDM), is proposed for the sixth generation of communications. As the initial study on this…

By adopting a divide-and-conquer strategy, subsystem-DFT (sDFT) can dramatically reduce the computational cost of large-scale electronic structure calculations. The key ingredients of sDFT are the nonadditive kinetic energy and…

The exponential emergence of Field Programmable Gate Array (FPGA) has accelerated the research of hardware implementation of Deep Neural Network (DNN). Among all DNN processors, domain specific architectures, such as, Google's Tensor…

The growing demands of distributed learning on resource constrained edge devices underscore the importance of efficient on device model compression. Tensor Train Decomposition (TTD) offers high compression ratios with minimal accuracy loss,…

This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing…