This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-of-two FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.
@article{arxiv.1905.08239,
title = {Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture},
author = {Jakub Žádník and Jarmo Takala},
journal= {arXiv preprint arXiv:1905.08239},
year = {2019}
}