Related papers: Active inductor shunt peaking in high-speed VCSEL …

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\mu$W in 0.35$\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for…

We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate.…

Pixel sensors based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the outer layer of the ATLAS inner tracker upgrade at the High Luminosity LHC. Here, charged particles are detected…

This paper presents a PVT-resilient, subthreshold SRAM-based computing-in-memory (CIM) macro tailored for energy-efficient spiking neural networks (SNNs). The macro integrates in-situ current sensors and distributed voltage regulators to…

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07% X/X$_{0}$ per layer and have a low power consumption…

Monolithic Active Pixel Sensors (MAPS) combine the sensing part and the front-end electronics in the same silicon layer, making use of CMOS technology. Profiting from the progresses of this commercial process, MAPS have been undergoing…

We present an R&D activity focused on the development of novel modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The modules consist of n-in-p pixel sensors, 100 or 200 $\mu$m thick, produced at VTT…

The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed to enable high frame rate readout of Skipper CCD-in-CMOS image sensors. The SPROCKET2 pixel is fabricated in a 65 nm CMOS process and occupies a 60$\mu$m $\times$…

The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms. However, existing AES hardware accelerators often face limitations in performance, energy…

Saturn is a dual-purpose accelerator. It can be operated as a large-area flash x-ray source for simulation testing or as a Z-pinch driver especially for K-line x-ray production. In the first mode, the accelerator is fitted with three…

Modern general-purpose accelerators integrate a large number of programmable area- and energy-efficient processing elements (PEs), to deliver high performance while meeting stringent power delivery and thermal dissipation constraints. In…

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a…

ALICE (A Large Ion Collider Experiment) experiment at CERN LHC is designed to study the properties of the Quark-Gluon Plasma (QGP) in heavy-ion collisions. In 2019-2020 the upgrade of CERN LHC will increase the luminosity and the collision…

The two innermost layers of the ALICE inner tracking system are instrumented with silicon pixel detectors. Single chip assembly prototypes of the ALICE pixels have been tested in high energy particle beams at the CERN SPS. Detection…

This paper describes a highly-integrated CMOS system-on-chip (SoC) for active structural health monitoring (SHM). The chip integrates ultrasonic power and bidirectional half-duplex data transfer, a power management unit (PMU), and an…

All Spin Logic gates employ multiple nano-magnets interacting through spin-torque using non-magnetic channels. Compactness, non-volatility and ultra-low voltage operation are some of the attractive features of ASL, while, low…

We report on the experimental study made on a successive prototype of High-Voltage CMOS (HV-CMOS) ATLASPix2 sensor for the tracking detector application, developed with 180 nm feature size. These sensors are to qualify mainly the peripheral…

Most active quench circuits used for single-photon avalanche detectors are designed either with discrete components which lack the flexibility of dynamically changing the control parameters, or with custom ASICs which require a long…

The integration of a Verticle Cavity Surface-Emitting Laser (VCSEL) array and a driving Application-Specific Integrated Circuit (ASIC) in a custom optical array transmitter module (ATx) for operation in the detector front-end is…

The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of resolution where the only given ones. Although…