Related papers: Implementation of mean-timing and subsequent logic…

Today's hardware technology presents a new challenge in designing robust systems. Deep submicron VLSI technology introduced transient and permanent faults that were never considered in low-level system designs in the past. Still, robustness…

During the High Luminosity LHC, the CMS detector will need charged particle tracking at the hardware trigger level to maintain a manageable trigger rate and achieve its physics goals. The tracklet approach is a track-finding algorithm based…

Sub-categories of mathematical topology, like the mathematical theory of chaos, offer interesting applications devoted to information security. In this research work, we have introduced a new chaos-based pseudorandom number generator…

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA…

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock…

Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity…

Several ways to electronically synchronize different types of amplified femtosecond laser systems are presented, based on a single freely programmable electronics hardware: Arbitrary-detuning asynchronous optical sampling, as well as…

The current algorithms are based on linear model, for example, Precision Time Protocol (PTP) which requires frequent synchronization in order to handle the effects of clock frequency drift. This paper introduces a nonlinear approach to…

A trigger system of general function is designed using the commercial module CAEN V2495 for heavy ion nuclear reaction experiment at Fermi energies. The system has been applied and verified on CSHINE (Compact Spectrometer for Heavy IoN…

Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely…

In recent years, quantum Ising machines have drawn a lot of attention, but due to physical implementation constraints, it has been difficult to achieve dense coupling, such as full coupling with sufficient spins to handle practical…

A field programmable gate array (FPGA) based timing and trigger control system has been developed for the Dynamic Compression Sector (DCS) user facility located at the Advanced Photon Source (APS) at Argonne National Laboratory. The DCS is…

This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks…

An automatic clock synchronizing method implemented in field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (ETOF) upgrade of the Beijing…

In this work we evaluate the potential of FPGAs for accelerating HPC workloads as a more power-efficient alternative to GPUs. Using High-Level Synthesis and a large set of optimization techniques, we show that FPGAs can achieve better…

Machine learning techniques have opened new avenues for real-time quantum state tomography (QST). In this work, we demonstrate the deployment of machine learning-based QST onto edge devices, specifically utilizing field programmable gate…

We present concept and implementation of a self-stabilizing Byzantine fault-tolerant distributed clock generation scheme for multi-synchronous GALS architectures in critical applications. It combines a variant of a recently introduced…

The Kaos spectrometer is maintained by the A1 collaboration at the Mainz Microtron MAMI with a focus on the study of (e,e'K^+) coincidence reactions. For its electron-arm two vertical planes of fiber arrays, each comprising approximately 10…

In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog…

In the context of embedded systems design, two important challenges are still under investigation. First, improve real-time data processing, reconfigurability, scalability, and self-adjusting capabilities of hardware components. Second,…