This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.
Cite
@article{arxiv.0710.4763,
title = {Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality},
author = {Matthias Beck and Olivier Barondeau and Martin Kaibel and Frank Poehl and Xijiang Lin and Ron Press},
journal= {arXiv preprint arXiv:0710.4763},
year = {2011}
}
Comments
Submitted on behalf of EDAA (http://www.edaa.com/)