Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT, in order to maximize the test throughput for a given SOC and ATE. The on-chip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC Test Benchmarks.
@article{arxiv.0710.4687,
title = {On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips},
author = {Sandeep Kumar Goel and Erik Jan Marinissen},
journal= {arXiv preprint arXiv:0710.4687},
year = {2011}
}
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