Related papers: Intrinsic Reliability improvement in Biaxially Str…
A fundamental obstacle toward the realization of GaN p-channel transistors is its low hole mobility. Here we investigate the intrinsic phonon-limited mobility of electrons and holes in wurtzite GaN using the ab initio Boltzmann transport…
Strain engineering provides an effective way of tailoring the electronic and optoelectronic properties of semiconductor nanomaterials and nanodevices, giving rise to novel functionalities. Here, we present direct experimental evidence of…
Stacking multiple SiSiGe channels in advanced logic devices faces severe thermal budget accumulation, which degrades interfaces via Ge-Si interdiffusion and strain relaxation.This strategy lowers the Ge diffusion coefficient to 5.6-7% of…
Strained Ge ($\epsilon$-Ge) and strained Si ($\epsilon$-Si) buried quantum wells have enabled advanced spin-qubit quantum processors. However, in the absence of suitable lattice-matched substrates, $\epsilon$-Ge and $\epsilon$-Si are…
We grow $^{28}$Si/SiGe heterostructures by reduced-pressure chemical vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500…
As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport…
In this work, single-layer intrinsic and fluorinated graphene were investigated as gate insertion layers in normally-OFF p-GaN gate HEMTs, which wraps around the bottom of the gate forming Ti/graphene/p-GaN at the bottom and Ti/graphene/…
Ambipolar currents in Germanium p-type nanowire Schottky barrier MOSFETs were calculated fully quantum-mechanically by using the multi-band k.p method and the non-equilibrium Green's function approach. We investigated the performance of…
In the present work, we have investigated the performances of p plus minus Al0.3Ga0.7Sb Pocket Implanted L shaped GaSb InAs staggered bandgap SG heterojunction vertical n channel tunnel field effect transistors TFETs of 4 nm thin channel…
We present a computational study on the impact of tensile/compressive uniaxial ($\varepsilon_{xx}$) and biaxial ($\varepsilon_{xx}=\varepsilon_{yy}$) strain on monolayer MoS$_{2}$ NMOS and PMOS FETs. The material properties like band…
Silicon nanowires (Si NW) are ideal candidates for solution processable field effect transistors (FETs). The interface between the nanowire channel and the gate dielectric plays a crucial role in the FET performance, and it can be…
We investigate carrier transport in a single 22 nm-thick double-gated Si quantum well device, which has independent contacts to electrons and holes. Conductance, Hall density and Hall mobility are mapped in a broad double-gate voltage…
Buried-channel semiconductor heterostructures are an archetype material platform to fabricate gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface, however nearby surface…
We investigated the electronic properties of strained Si/Ge core-shell nanowires along the [110] direction using first principles calculations based on density-functional theory. The diameter of the studied core-shell wire is up to 5 nm. We…
In this paper, Capacitance-Voltage (C-V) characteristics and direct tunneling (DT) gate leakage current of antimonide based surface channel MOSFET were investigated. Self-consistent method was applied by solving coupled…
We grow strained Ge/SiGe heterostructures by reduced-pressure chemical vapor deposition on 100 mm Ge wafers. The use of Ge wafers as substrates for epitaxy enables high-quality Ge-rich SiGe strain-relaxed buffers with a threading…
A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as $\rm SiO_2$,…
A gate voltage application in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) modulates spin accumulation voltages, where both electrical conductivity and drift velocity are modified while keeping constant…
In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI LDMOS with an extended-p+ region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact…
We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge0.96Sn0.04 nanowire MOSFETs (NWFETs) were simulated using rigorous ballistic quantum…