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Impedance models are widely used in assessing small signal stability of grid-tied voltage source converter (VSC) systems. Recent research has proven that impedance models of grid-tied VSC in both dq and sequence domains are generally…
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing…
Silicon-based waveguide plasmon detectors have a great research interest because of CMOS compatibility and integration capability with other plasmonic integrated circuits. In this paper, a balanced metal-semiconductor-metal (MSM) integrated…
We have used a simple, analytically solvable model to analyze the characteristic s of dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with 10-nm-scale channel length L. The model assumes ballistic dynamics of 2D…
During the dielectric breakdown process of thin solid-state nanopores, the application of high voltages may cause the formation of multi-nanopores on one chip, which number and sizes are important for their applications. Here, simulations…
In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided…
Accurate and efficient circuit behavior modeling is a cornerstone of modern electronic design automation. Among different types of circuits, stiff circuits are challenging to model using previous frameworks. In this work, we propose a new…
In this work, the source structure of an n-type thin-film tunneling FET is engineered to get better performance. An ultra-thin SiGe along with Si is used in the source of silicon-based TFET. Two structures are compared with conventional…
Strain engineering has played a key role in modern silicon electronics, having been introduced as a mobility booster in the 1990s and commercialized in the early 2000s. Achieving similar advances with two-dimensional (2D) semiconductors in…
A real-space quantum transport simulator for carbon nanoribbon (CNR) MOSFETs has been developed. Using this simulator, the performance of carbon nanoribbon (CNR) MOSFETs is examined in the ballistic limit. The impact of quantum effects on…
Silicon carbide (SiC) metal-oxide-semiconductor field-effect-transistors (MOSFETs) enable high-voltage and high-temperature power conversion. Compared to Si devices, they suffer from pronounced gate leakage due to the reduced electron…
The MOS devices are the basic building block of any digital and analog circuits, where silicon (Si) is the most commonly used material. The International Technology Roadmap Semiconductor (ITRS) report predicts the gate length of the MOS…
Advancing complementary metal-oxide-semiconductor (CMOS) technology into the sub-1-nm angstr\"om-scale technology nodes is expected to involve alternative semiconductor channel materials, as silicon transistors encounter severe performance…
This work presents a theoretical and numerical study of electrokinetic flow and the zeta potential for the case of slit channels with nanoscale roughness of dimensions comparable to the Debye length, by employing molecular dynamics…
We present a modeling approach based on the BSIM-IMG compact model to capture the deep-cryogenic behavior of MOSFET devices in a 22-nm FDSOI technology. The modeling flow is based on DC measurements to extract static parameters including…
In this paper we present a new multi-scale simulation scheme for next-generation electronic design automation for nano-electronics. The scheme features a combination of the first-principles quantum mechanical calculation, semi-classical…
This paper examines the validity of the widely-used parabolic effective-mass approximation for computing the current-voltage (I-V) characteristics of silicon nanowire transistors (SNWTs). The energy dispersion relations for unrelaxed Si…
We depict the use of x-ray diffraction as a tool to directly probe the strain status in rolled-up semiconductor tubes. By employing continuum elasticity theory and a simple model we are able to simulate quantitatively the strain relaxation…
We demonstrate the fabrication of graphene nanogap with crystallographically matching edges on SiO2Si substrates by divulsion. The current-voltage measurement is then performed in a high-vacuum chamber for a graphene nanogap with few…
After more than 30 years of validation of Moore's law, the CMOS technology has already entered the nanoscale (sub-100nm) regime and faces strong limitations. The nanowire transistor is one candidate which has the potential to overcome the…