Related papers: Catalyst preparation for CMOS-compatible silicon n…
Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…
We study the effect of synthesis temperature on the phase formation in nano(n)-SiC added bulk MgB2 superconductor. In particular we study: lattice parameters, amount of carbon (C) substitution, microstructure, critical temperature (Tc),…
Inelastic electron tunneling and surface-enhanced optical spectroscopies at the molecular scale require cryogenic local temperatures even under illumination - conditions that are challenging to achieve with plasmonically resonant metallic…
The ability to integrate carbon nanotubes, especially single-walled carbon nanotubes, seamlessly onto silicon would expand the range of applications considerably. Though direct integration using chemical vapor deposition is the simplest…
Accurate on-chip temperature sensing is critical for the optimal performance of modern CMOS integrated circuits (ICs), to understand and monitor localized heating around the chip during operation. The development of quantum computers has…
Superconducting nanowires, with a critical temperature of 5.2 K, have been synthesized using an ion-beam-induced deposition, with a Gallium focused ion beam and Tungsten Carboxyl, W(CO)6, as precursor. The films are amorphous, with atomic…
A high temperature for some catalytic reactions like synthesis of large area and high quality graphene is required. The mentioned graphene can be obtained by a chemical vapour deposition (CVD) process on copper foil at 800 1000. Here, we…
Graphene ranks highly as a possible material for future high-speed and flexible electronics. Current fabrication routes, which rely on metal substrates, require post synthesis transfer of the graphene onto a Si wafer or in the case of…
This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel…
The thermal conductivity of silicon nanowires (SiNWs) is investigated by molecular dynamics (MD) simulation. It is found that the thermal conductivity of SiNWs can be reduced exponentially by isotopic defects at room temperature. The…
In this study, the synthesis of multi-walled carbon nanotubes (MWCNTs) was carried out by chemical vapor deposition (CVD) using propane as the carbon source and Si as the catalyst support. The effect of CVD process variables such as…
Various diameters of alumina-supported Fe catalysts are used to grow single-walled carbon nanotubes (SWCNTs) with chemical vapor decomposition. We find that the reduction of the catalyst size requires an increase of the minimum temperature…
Low dimensional systems, nanowires, in particular, have exhibited excellent optical and electronic properties. Understanding the thermal properties in semiconductor nanowires is very important for their applications in their electronic…
This thesis is dedicated to the synthesis, characterization and the study of electrical transport through metal nanowires and nanotubes. The metal nanowires(Ni, Cu) and nanotubes(Cu) are synthesised by electrochemical deposition in…
A constant supply of oxygen has been assumed to be necessary for the growth of titanium nanoparticles by sputtering. This oxygen supply can arise from a high background pressure in the vacuum system or from a purposely supplied gas. The…
In this research a novel and simple electrochemical method is developed in order to facilitate the large-scale production of nanowires. The proposed electrochemical technique shows versatile controllability over chemical composition and…
Nanoporosity in silicon results in an interface-dominated mechanics, fluidics and photonics that are often superior to the ones of the bulk material. However, their active control, e.g. as a response to electronic stimuli, is challenging…
Doping is a common route to reducing nanowire transistor on-resistance but has limits. High doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even…
The nucleation and growth of CdS nanoparticles within a polymer matrix was followed by in-situ synchrotron X-ray diffraction. The nanoparticles form by effect of the thermolysis of thiolate precursors at temperatures between 200 and 300…
Large power consumption of silicon CMOS electronics is a challenge in very-large-scale integrated circuits and a major roadblock to fault-tolerant quantum computation. Matching the power dissipation of Si-MOSFETs to the thermal budget at…