Related papers: PARISROC, a photomultiplier array readout chip
The dual-radiator RICH (dRICH) detector of the ePIC experiment will employ over 300000 SiPM pixels as photosensors, organized into more than 1000 Photon Detection Units. Each PDU is a compact module, approximately 5x5x12 cm^3 in size,…
Calorimetry at future linear colliders could be based on a particle flow approach where granularity is the key to high jet energy resolution. Among different technologies, Micromegas chambers with 1 cm2 pad segmentation are studied for the…
Modern PET scanners based on scintillating crystals use solid state photo detectors for light readout. The small area of these devices is beneficial for spatial resolution, but also leads to a large number of electronic channels to be read…
The ForwArd Search ExpeRiment (FASER) is an experiment searching for new light and weakly-interacting particles at CERN's Large Hadron Collider. FASER is composed of different sub-detectors, including silicon microstrip detectors,…
A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The…
Reservoir computing, renowned for its low training cost, has emerged as a promising lightweight paradigm for efficient spatiotemporal processing,it remains challenging to realize deep photonic reservoir computing (DPRC) systems, due to the…
Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within the framework of the Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence of 1 x 1016 neq/cm2, and then tested using a…
The development of large-area homogeneous photo-detectors with sub-millimeter path lengths for direct Cherenkov light and for secondary-electrons opens the possibility of large time-of-flight systems for relativistic particles with…
This work presents the first measurements performed on the Timespot1 ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32x32 channels hybrid-pixel matrix. Targeted to space-time tracking applications in…
ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs…
We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the…
We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode…
While designed primarily for X-ray imaging applications, the Medipix3 ASIC can also be used for charged-particle tracking. In this work, results from a beam test at the CERN SPS with irradiated and non-irradiated sensors are presented and…
This paper presents the design, implementation, and performance evaluation of LUCAS, a low-power, ultra-low jitter ASIC optimized for SiPM readout in Time-of-Flight Computed Tomography (ToF-CT) applications. Leveraging a novel preamplifier…
The first generation of Single electron Sensitive Read Out (SiSeRO) amplifiers, employed as on-chip charge detectors for charge-coupled devices (CCDs) have demonstrated excellent noise and spectral performance: a responsivity of around 800…
Combining gaseous detectors with a high-granularity pixelated charge readout enables experimental applications which otherwise could not be achieved. This includes high-resolution tracking of low-energetic particles, requiring ultra-low…
Silicon photomultiplier (SiPM), a new type of photosensor, is considered a substitute for traditional photomultiplier tube (PMT) in the next generation of dark matter and neutrino detectors, especially in noble gas detectors like liquid…
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…
Three generations of full-custom analog integrated circuits designed for low-power, high-speed sampling of Radio-Frequency (RF) transients in excess of the Nyquist minimum have been developed. These 0.25$\mu m$ CMOS devices are denoted the…
The design and evaluation on the NSLS-II beamline of the 3FI application specific integrated circuit (ASIC) bump-bonded to a simply, planar, two-dimensionally segmented silicon sensor is presented. The ASIC was developed for Full-Field…