Network coding enhances performance in network communications and distributed storage by increasing throughput and robustness while reducing latency. Batched Sparse (BATS) codes are a class of capacity-achieving network codes, but their practical applications are hindered by their structure, computational intensity, and power demands of finite field operations. Most literature focuses on algorithmic-level techniques to improve coding efficiency. Optimization with an algorithm/hardware co-designing approach has long been neglected. Leveraging the unique structure of BATS codes, we first present CS-BATS, a hardware-friendly variant. Next we propose a simple but effective bounded-value generator, to reduce the size of a finite field multiplier by up to 70%. Finally, we report on a scalable and resource-efficient FPGA-based network coding accelerator that achieves a throughput of 27 Gbps, a speedup of more than 300 over software.
@article{arxiv.2501.05033,
title = {Towards High-Performance Network Coding: FPGA Acceleration With Bounded-value Generators},
author = {Jiaxin Qing and Philip H. W. Leong and Kin Hong Lee and Raymond W. Yeung},
journal= {arXiv preprint arXiv:2501.05033},
year = {2025}
}