Convolutional neural network (CNN) accelerators implemented on Field-Programmable Gate Arrays (FPGAs) are typically designed with a primary focus on maximizing performance, often measured in giga-operations per second (GOPS). However, real-life embedded deep learning (DL) applications impose multiple constraints related to latency, power consumption, area, and cost. This work presents a hardware-software (HW/SW) co-design methodology in which a CNN accelerator is described using high-level synthesis (HLS) tools that ease the parameterization of the design, facilitating more effective optimizations across multiple design constraints. Our experimental results demonstrate that the proposed design methodology is able to outperform non-parameterized design approaches, and it can be easily extended to other types of DL applications.
@article{arxiv.2602.04044,
title = {A Parameterizable Convolution Accelerator for Embedded Deep Learning Applications},
author = {Panagiotis Mousouliotis and Georgios Keramidas},
journal= {arXiv preprint arXiv:2602.04044},
year = {2026}
}
Comments
6 pages, 4 figures. Published in the proceedings of the 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2025), Kalamata, Greece, 6-9 July 2025