We investigate by low-temperature transport experiments the sub-threshold behavior of triple-gate silicon field-effect transistors. These three-dimensional nano-scale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers, down to 50x60x35 nm^3. Conductance versus gate voltage show Coulomb-blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analysis, we conclude that sub-threshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner-effect.
@article{arxiv.cond-mat/0603430,
title = {Sub-threshold channels at the edges of nanoscale triple-gate silicon transistors},
author = {H. Sellier and G. P. Lansbergen and J. Caro and N. Collaert and I. Ferain and M. Jurczak and S. Biesemans and S. Rogge},
journal= {arXiv preprint arXiv:cond-mat/0603430},
year = {2009}
}