Protect Your Chip Design Intellectual Property: An Overview
Abstract
The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work.
Keywords
Cite
@article{arxiv.1902.05333,
title = {Protect Your Chip Design Intellectual Property: An Overview},
author = {Johann Knechtel and Satwik Patnaik and Ozgur Sinanoglu},
journal= {arXiv preprint arXiv:1902.05333},
year = {2019}
}
Comments
INTERNATIONAL CONFERENCE ON OMNI-LAYER INTELLIGENT SYSTEMS (COINS), May 5--7, 2019, Crete, Greece; 6 pages, 3 figures, 1 table; [v2]: minor edits and update references, as in camera copy for COINS; [v3]: added ACM reference format and CCS concepts, minor edits