CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuitry layout and impacting efficiency via ballistic deficit.
@article{arxiv.2503.21853,
title = {Impact of the circuit layout on the charge collection in a monolithic pixel sensor},
author = {Corentin Lemoine and Rafael Ballabriga and Eric Buschmann and Michael Campbell and Raimon Casanova Mohr and Dominik Dannheim and Jona Dilg and Ana Dorda and Finn King and Ono Feyens and Philipp Gadow and Ingrid-Maria Gregor and Karsten Hansen and Yajun He and Lennart Huth and Iraklis Kremastiotis and Stefano Maffessanti and Larissa Mendes and Younes Otarid and Christian Reckleben and Sébastien Rettie and Manuel Alejandro del Rio Viera and Sara Ruiz Daza and Judith Schlaadt and Adriana Simancas and Walter Snoeys and Simon Spannagel and Tomas Vanat and Anastasiia Velyka and Gianpiero Vignola and Håkan Wennlöf},
journal= {arXiv preprint arXiv:2503.21853},
year = {2025}
}
Comments
Presented at the Eleventh International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (Nov 18-22 2024, Strasbourg, France). Submitted to JINST