Characterisation of analogue MAPS produced in the 65 nm TPSCo process

Within the context of the ALICE ITS3 collaboration, a set of MAPS small-scale test structures were developed using the 65 nm TPSCo CMOS imaging process with the upgrade of the ALICE inner tracking system as its primary focus. One such sensor, the Circuit Exploratoire 65 nm (CE-65), and its evolution the CE-65v2, were developed to explore charge collection properties for varying configurations including collection layer process (standard, blanket, modified with gap), pixel pitch (15, 18, \SI{22.5}{\micro\meter}), and pixel geometry (square vs hexagonal/staggered). In this work the characterisation of the CE-65v2 chip, based on $^{55}$Fe lab measurements and test beams at CERN SPS, is presented. Matrix gain uniformity up to the $\mathcal{O}$(5\%) level was demonstrated for all considered chip configurations. The CE-65v2 chip achieves a spatial resolution of under \SI{2}{\micro\meter} during beam tests. Process modifications allowing for faster charge collection and less charge sharing result in decreased spatial resolution, but a considerably wider range of operation, with both the \SI{15}{\micro\meter} and \SI{22.5}{\micro\meter} chips achieving over 99\% efficiency up to a $\sim$180 e$^{-}$ seed threshold. The results serve to validate the 65 nm TPSCo CMOS process, as well as to motivate design choices in future particle detection experiments.