In this research communication, we comment on "Dual-rail asynchronous logic multi-level implementation" [Integration, the VLSI Journal 47 (2014) 148-159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.
Cite
@article{arxiv.1802.00004,
title = {Comments on "Dual-rail asynchronous logic multi-level implementation"},
author = {P Balasubramanian},
journal= {arXiv preprint arXiv:1802.00004},
year = {2018}
}