The new vision presented is aimed to overcome the logic overhead issues that previous works exhibit when applying GALS techniques to programmable logic devices. The proposed new view relies in a 2-phase, bundled data parity based protocol for data transfer and clock generation tasks. The ability of the introduced methodology for smart real-time delay selection allows the implementation of a variety of new methodologies for electromagnetic interference mitigation and device environment changes adaptation.
@article{arxiv.0802.3441,
title = {Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach},
author = {Javier D. Garcia-Lasheras},
journal= {arXiv preprint arXiv:0802.3441},
year = {2008}
}
Comments
English version of the paper presented in the Spanish Workshop on Reconfigurable Computing and Applications, Zaragoza (2007)