English

Chip-level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films

Computational Engineering, Finance, and Science 2007-05-23 v1

Abstract

Chip-level CMP modeling is investigated to obtain the post-CMP film profile thickness across a die from its design layout file and a few film deposition and CMP parameters. The work covers both HDP and conformal CVD film. The experimental CMP results agree well with the modeled results. Different algorithms for filling of dummy structure are compared. A smart algorithm for dummy filling is presented, which achieves maximal pattern-density uniformity and CMP planarity.

Cite

@article{arxiv.cs/0011014,
  title  = {Chip-level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films},
  author = {George Yong Liu and Ray F. Zhang and Kelvin Hsu and Lawrence Camilletti},
  journal= {arXiv preprint arXiv:cs/0011014},
  year   = {2007}
}

Comments

10 pages, 7 figures; for used software, see http://www.cmptechnology.com/

R2 v1 2026-07-22T12:18:32.001Z