This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.
@article{arxiv.0710.4762,
title = {Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction},
author = {Takeshi Kitahara and Naoyuki Kawabe and Fimihiro Minami and Katsuhiro Seta and Toshiyuki Furusawa},
journal= {arXiv preprint arXiv:0710.4762},
year = {2011}
}
Comments
Submitted on behalf of EDAA (http://www.edaa.com/)