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A Custom 7nm CMOS Standard Cell Library for Implementing TNN-based Neuromorphic Processors

Hardware Architecture 2021-06-08 v2 Emerging Technologies Machine Learning Neural and Evolutionary Computing

Abstract

A set of highly-optimized custom macro extensions is developed for a 7nm CMOS cell library for implementing Temporal Neural Networks (TNNs) that can mimic brain-like sensory processing with extreme energy efficiency. A TNN prototype (13,750 neurons and 315,000 synapses) for MNIST requires only 1.56mm2 die area and consumes only 1.69mW.

Keywords

Cite

@article{arxiv.2012.05419,
  title  = {A Custom 7nm CMOS Standard Cell Library for Implementing TNN-based Neuromorphic Processors},
  author = {Harideep Nair and Prabhu Vellaisamy and Santha Bhasuthkar and John Paul Shen},
  journal= {arXiv preprint arXiv:2012.05419},
  year   = {2021}
}

Comments

This work is dated and will be superseded by a forthcoming work

R2 v1 2026-06-23T20:51:41.109Z