XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks
Computer Vision and Pattern Recognition2018-09-12v1Artificial IntelligenceHardware ArchitectureNeural and Evolutionary ComputingImage and Video Processing
Deploying state-of-the-art CNNs requires power-hungry processors and off-chip memory. This precludes the implementation of CNNs in low-power embedded systems. Recent research shows CNNs sustain extreme quantization, binarizing their weights and intermediate feature maps, thereby saving 8-32\x memory and collapsing energy-intensive sum-of-products into XNOR-and-popcount operations. We present XNORBIN, an accelerator for binary CNNs with computation tightly coupled to memory for aggressive data reuse. Implemented in UMC 65nm technology XNORBIN achieves an energy efficiency of 95 TOp/s/W and an area efficiency of 2.0 TOp/s/MGE at 0.8 V.
@article{arxiv.1803.05849,
title = {XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks},
author = {Andrawes Al Bahou and Geethan Karunaratne and Renzo Andri and Lukas Cavigelli and Luca Benini},
journal= {arXiv preprint arXiv:1803.05849},
year = {2018}
}