Optimization of applications for supercomputers of the highest performance class requires parallelization at multiple levels using different techniques. In this contribution we focus on parallelization of particle physics simulations through vector instructions. With the advent of the Scalable Vector Extension (SVE) ISA, future ARM-based processors are expected to provide a significant level of parallelism at this level.
@article{arxiv.1901.07294,
title = {SVE-enabling Lattice QCD Codes},
author = {Nils Meyer and Peter Georg and Dirk Pleiter and Stefan Solbrig and Tilo Wettig},
journal= {arXiv preprint arXiv:1901.07294},
year = {2019}
}