English

Small hitting-sets for tiny arithmetic circuits or: How to turn bad designs into good

Computational Complexity 2017-02-24 v1

Abstract

We show that if we can design poly(ss)-time hitting-sets for ΣaΣΠO(logs)\Sigma\wedge^a\Sigma\Pi^{O(\log s)} circuits of size ss, where a=ω(1)a=\omega(1) is arbitrarily small and the number of variables, or arity nn, is O(logs)O(\log s), then we can derandomize blackbox PIT for general circuits in quasipolynomial time. This also establishes that either E⊈\not\subseteq\#P/poly or that VP\neVNP. In fact, we show that one only needs a poly(ss)-time hitting-set against individual-degree a=ω(1)a'=\omega(1) polynomials that are computable by a size-ss arity-(logs)(\log s) ΣΠΣ\Sigma\Pi\Sigma circuit (note: Π\Pi fanin may be ss). Alternatively, we claim that, to understand VP one only needs to find hitting-sets, for depth-33, that have a small parameterized complexity. Another tiny family of interest is when we restrict the arity n=ω(1)n=\omega(1) to be arbitrarily small. We show that if we can design poly(s,μ(n)s,\mu(n))-time hitting-sets for size-ss arity-nn ΣΠΣ\Sigma\Pi\Sigma\wedge circuits (resp.~ΣaΣΠ\Sigma\wedge^a\Sigma\Pi), where function μ\mu is arbitrary, then we can solve PIT for VP in quasipoly-time, and prove the corresponding lower bounds. Our methods are strong enough to prove a surprising {\em arity reduction} for PIT-- to solve the general problem completely it suffices to find a blackbox PIT with time-complexity sd2O(n)sd2^{O(n)}. We give several examples of (logs\log s)-variate circuits where a new measure (called cone-size) helps in devising poly-time hitting-sets, but the same question for their ss-variate versions is open till date: For eg., diagonal depth-33 circuits, and in general, models that have a {\em small} partial derivative space. We also introduce a new concept, called cone-closed basis isolation, and provide example models where it occurs, or can be achieved by a small shift.

Cite

@article{arxiv.1702.07180,
  title  = {Small hitting-sets for tiny arithmetic circuits or: How to turn bad designs into good},
  author = {Manindra Agrawal and Michael Forbes and Sumanta Ghosh and Nitin Saxena},
  journal= {arXiv preprint arXiv:1702.07180},
  year   = {2017}
}

Comments

25 pages, No figures

R2 v1 2026-06-22T18:26:20.933Z