Although we may be at the end of Moore's law, lowering chip power consumption is still the primary driving force for the designers. To enable low-power operation, we propose a resonant energy recovery static random access memory (SRAM). We propose the first series resonance scheme to reduce the dynamic power consumption of the SRAM operation. Besides, we identified the requirement of supply boosting of the write buffers for proper resonant operation. We evaluated the resonant 144KB SRAM cache through SPICE and test chip using a commercial 28nm CMOS technology. The experimental results show that the resonant SRAM can save up to 30% dynamic power at 1GHz operating frequency compared to the state-of-the-art design.
@article{arxiv.2010.01767,
title = {Resonant Energy Recycling SRAM Architecture},
author = {Riadul Islam and Biprangshu Saha and Ignatius Bezzam},
journal= {arXiv preprint arXiv:2010.01767},
year = {2020}
}
Comments
This paper is accepted to IEEE Transactions on Circuits and Systems--II