Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography
Abstract
Triple patterning lithography (TPL) has been recognized as one of the most promising solutions to print critical features in advanced technology nodes. A critical challenge within TPL is the effective assignment of the layout to masks. Recently, various layout decomposition methods and TPL-aware routing methods have been proposed to consider TPL. However, these methods typically result in numerous conflicts and stitches, and are mainly designed for 2-pin nets. This paper proposes a multi-pin net routing method in triple patterning lithography, called Mr.TPL. Experimental results demonstrate that Mr.TPL reduces color conflicts by 81.17%, decreases stitches by 76.89%, and achieves up to 5.4X speed improvement compared to the state-of-the-art TPL-aware routing method.
Cite
@article{arxiv.2412.02703,
title = {Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography},
author = {Chengkai Wang and Weiqing Ji and Mingyang Kou and Zhiyang Chen and Fei Li and Hailong Yao},
journal= {arXiv preprint arXiv:2412.02703},
year = {2026}
}