This paper presents the FPGA hardware design of a turbo decoder for the cdma2000 standard. The work includes a study and mathematical analysis of the turbo decoding process, based on the MAX-Log-MAP algorithm. Results of decoding for a packet size of two hundred fifty bits are presented, as well as an analysis of area versus performance, and the key variables for hardware design in turbo decoding.
@article{arxiv.1404.5929,
title = {FPGA design of a cdma2000 turbo decoder},
author = {Maribell Sacanamboy Franco and Fabio G. Guerrero},
journal= {arXiv preprint arXiv:1404.5929},
year = {2014}
}