Parallel Interleaver Design for a High Throughput HSPA+/LTE Multi-Standard Turbo Decoder
Abstract
To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA+/LTE/LTE-Advanced multi-standard turbo decoder with a 45nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm^2. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.
Cite
@article{arxiv.1403.3759,
title = {Parallel Interleaver Design for a High Throughput HSPA+/LTE Multi-Standard Turbo Decoder},
author = {Guohui Wang and Hao Shen and Yang Sun and Joseph R. Cavallaro and Aida Vosoughi and Yuanbin Guo},
journal= {arXiv preprint arXiv:1403.3759},
year = {2014}
}
Comments
14 pages, 15 figures. Accepted for publication by IEEE Transactions on Circuits and Systems I: Regular Papers