Hardware efficient transpilation of quantum circuits to a quantum devices native gateset is essential for the execution of quantum algorithms on noisy quantum computers. Typical quantum devices utilize a gateset with a single two-qubit Clifford entangling gate per pair of coupled qubits, however, in some applications access to a non-Clifford two-qubit gate can result in more optimal circuit decompositions and also allows more flexibility in optimizing over noise. We demonstrate calibration of a low error non-Clifford Controlled-2π phase (CS) gate on a cloud based IBM Quantum computing using the Qiskit Pulse framework. To measure the gate error of the calibrated CS gate we perform non-Clifford CNOT-Dihedral interleaved randomized benchmarking. We are able to obtain a gate error of 5.9(7)×10−3 at a gate length 263 ns, which is close to the coherence limit of the associated qubits, and lower error than the backends standard calibrated CNOT gate.
@article{arxiv.2007.08532,
title = {Experimental implementation of non-Clifford interleaved randomized benchmarking with a controlled-S gate},
author = {Shelly Garion and Naoki Kanazawa and Haggai Landa and David C. McKay and Sarah Sheldon and Andrew W. Cross and Christopher J. Wood},
journal= {arXiv preprint arXiv:2007.08532},
year = {2021}
}
Comments
9 pages, 4 figures, references are updated, QPT curve in the Fig. 2 is updated based on new analysis procedure detailed in Appendix B. Conclusions unchanged