Fault-Tolerant Computing With Biased-Noise Superconducting Qubits
Abstract
We present a universal scheme of pulsed operations for the IBM oscillator-stabilized flux qubit comprising the CPHASE gate, single-qubit preparations and measurements. Based on numerical simulations, we argue that the error rates for these operations can be as low as about .5% and that noise is highly biased, with phase errors being stronger than all other types of errors by a factor of nearly 10^3. In contrast, the design of a CNOT gate for this system with an error rate of less than about 1.2% seems extremely challenging. We propose a special encoding which exploits the noise bias allowing us to implement a logical CNOT gate where phase errors and all other types of errors have nearly balanced rates of about .4%. Our results illustrate how the design of an encoding scheme can be adjusted and optimized according to the available physical operations and the particular noise characteristics of experimental devices.
Cite
@article{arxiv.0806.0383,
title = {Fault-Tolerant Computing With Biased-Noise Superconducting Qubits},
author = {Panos Aliferis and Frederico Brito and David P. DiVincenzo and John Preskill and Matthias Steffen and Barbara M. Terhal},
journal= {arXiv preprint arXiv:0806.0383},
year = {2009}
}
Comments
15 pages, 7 figures