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EMiX: Emulating Beyond Single-FPGA Limits

Hardware Architecture 2026-05-01 v1

Abstract

FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale multi-core systems increasingly exceed the hardware resource capacity of a single FPGA, limiting the feasibility of full-system emulation. To address this challenge, we introduce EMiX, a scalable multi-FPGA framework that enables distributed emulation of multi-core RISC-V architectures beyond single-FPGA resource limits. EMiX systematically partitions a monolithic multi-core design into multiple components and deploys them across multiple interconnected FPGAs, effectively exploiting inter-FPGA interconnects to balance scalability and performance without requiring fundamental RTL redesign. We prototype EMiX with a 64-core architecture across eight interconnected Alveo U55c FPGAs (scalable on core and FPGA counts), successfully demonstrating full-system execution including Linux boot. EMiX will be released as an open-source platform.

Keywords

Cite

@article{arxiv.2604.27012,
  title  = {EMiX: Emulating Beyond Single-FPGA Limits},
  author = {Alexander Kropotov and Miquel Moreto and Behzad Salami},
  journal= {arXiv preprint arXiv:2604.27012},
  year   = {2026}
}

Comments

RISC-V Summit EU 2026

R2 v1 2026-07-01T12:42:03.562Z