Validating FPGA firmware logic used in particle physics is becoming increasingly difficult as the implementation logic scales and becomes more complex with the expansion of FPGA resources. In order to address this issue efficiently, we have developed a firmware validation system utilizing an FPGA embedded on the PCI-express board, referred to as FPGA accelerators, produced by FPGA vendors. We developed a system that controls communication with DDR memory and runs logic on the FPGA. This system supports the use of firmware written in Hardware Description Language as well as High-Level Synthesis firmware, enabling rapid validation. This paper details the developed system and its significant improvements in validation speed and flexibility compared to traditional methods.
Cite
@article{arxiv.2503.18357,
title = {Development of the firmware logic validation system using the FPGA accelerator},
author = {Ryugo Mizuhiki and Junpei Maeda and Seiya Marumoto},
journal= {arXiv preprint arXiv:2503.18357},
year = {2025}
}
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TWEPP 2024 Conference This version matches the final accepted proceedings version to be published in JINST