Data logging at an upgraded KEKB accelerator or the J-PARC facility, currently under commission, requires a high density data acquisition platform with integrated data reduction CPUs. To follow market trends, we have developed a DAQ platform based on the PCI bus, a choice which permits a fast DAQ and a long expected lifetime of the system. The platform is a 9U-VME motherboard consisting of four slots for signal digitization modules, readout FIFOs for data buffering, and three PMC slots, on one of which resides a data reduction CPU. We have performed long term and thermal stability tests. The readout speed on the platform has been measured up to 125 MB/s in DMA mode.
@article{arxiv.hep-ex/0305088,
title = {Development of a PCI Based Data Acquisition Platform for High Intensity Accelerator Experiments},
author = {T. Higuchi and H. Fujii and M. Ikeno and Y. Igarashi and E. Inoue and R. Itoh and H. Kodama and T. Murakami and M. Nakao and K. Nakayoshi and M. Saitoh and S. Shimazaki and S. Y. Suzuki and M. Tanaka and K. Tauchi and M. Yamauchi and Y. Yasu and G. Varner and Y. Nagasaka and T. Katayama and K. Watanabe and M. Ishizuka and S. Onozawa and C. J. Li},
journal= {arXiv preprint arXiv:hep-ex/0305088},
year = {2007}
}
Comments
Talk from the 2003 Computing in High Energy and Nuclear Physics (CHEP03), La Jolla, Ca, USA, March 2003, 6 pages, LaTex, 7 eps figures. PSN TUGT004