Related papers: Development of an ASD IC for the Micro Pixel Chamb…
The LAB4D is a new application-specific integrated circuit (ASIC) of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) family, for use in direct wideband radio frequency digitization such as is used in…
This work presents the 8-channel FastIC+, a low-power consumption and highly configurable multi-channel front-end ASIC with internal digitization, for the readout of photo-sensors with picosecond time resolution and intrinsic gain. This…
This work presents an efficient ASIC implementation of successive cancellation (SC) decoder for polar codes. SC is a low-complexity depth-first search decoding algorithm, favorable for beyond-5G applications that require extremely high…
We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the…
The analog front-end electronics based on the constant fraction discrimination method is designed and optimized for the Multigap Resistive Plate Chamber (MRPC) timing measurements. The total time resolution of 40 ps has been obtained for 10…
Within the ATTRACT FASTPIX project, a monolithic pixel sensor demonstrator chip has been developed in a modified 180 nm CMOS imaging process technology, targeting sub-nanosecond timing precision for single ionising particles. It features a…
AXIS, a Probe mission concept now in a Phase A study, will provide transformative studies of high-energy astrophysical phenomena thanks to its high-resolution X-ray spectral imaging. These capabilities are enabled by improvements to the…
The TT-PET collaboration is developing a small animal TOF-PET scanner based on monolithic silicon pixel sensors in SiGe BiCMOS technology. The demonstrator chip, a small-scale version of the final detector ASIC, consists of a 3 x 10 pixel…
- This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage…
In this paper, we propose a high-precision SRAM-based CIM macro that can perform 4x4-bit MAC operations and yield 9-bit signed output. The inherent discharge branches of SRAM cells are utilized to apply time-modulated MAC and 9-bit ADC…
IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 16 x 16 pixels CdTe or CdZnTe pixelated detectors to build low power micro gamma camera. IDeF-X HD has been designed in the standard AMS…
The ATLAS Muon Spectrometer is undergoing a major upgrade for the High-Luminosity LHC (HL-LHC), including the addition of three new thin-gap Resistive Plate Chamber (RPC) layers in the inner barrel region. These RPCs have 1 mm gas gaps…
This paper presents a 125$\mu$W, area efficient (0.042mm2) 81dB DR, 8kS/s current sensing ADC in 45nm CMOS capable of sensing sub-pA currents. Our approach combines the transimpedance amplifier (TIA) and ADC into a unified structure by…
Readout chips of hybrid pixel detectors use a low power amplifier and threshold discrimination to process charge deposited in semiconductor sensors. Due to transistor mismatch each pixel circuit needs to be calibrated individually to…
Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a…
Analog-to-digital converters (ADCs) play a vital important role in any devices via manipulating analog signals in a digital manner. Given that the amplitude of the signal exceeds the dynamic range of the ADCs, clipping occurs and the…
We designed, produced, and tested RSD (Resistive AC-Coupled Silicon Detectors) devices, an evolution of the standard LGAD (Low-Gain Avalanche Diode) technology where a resistive n-type implant and a coupling dielectric layer have been…
To enable low-power and low-complexity wireless monitoring, an improved circuit design of Analog Joint Source Channel Coding (AJSCC) is proposed for wireless sensor nodes. This innovative design is based on Analog Divider Blocks (ADB) with…
The SAMpler for PICosecond time (SAMPIC) chip has been designed by a collaboration including CEA/IRFU/SEDI, Saclay and CNRS/LAL/SERDI, Orsay. It benefits from both the quick response of a time to digital converter and the versatility of a…
In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop…