Related papers: Improved performance of QCD code on ALiCE

Today's cluster computers suffer from slow I/O, which slows down I/O-intensive applications. We show that fast disk I/O can be achieved by operating a parallel file system over fast networks such as Myrinet or Gigabit Ethernet. In this…

Current generation solid-state storage devices are exposing a new bottlenecks in the SCSI and block layers of the Linux kernel, where IO throughput is limited by lock contention, inefficient interrupt handling, and poor memory locality. To…

We describe the construction of a high performance parallel computer composed of PC components, present some physical results for light hadron and hybrid meson masses from lattice QCD. We also show that the smearing technique is very useful…

Efficient Reduce and AllReduce communication collectives are a critical cornerstone of high-performance computing (HPC) applications. We present the first systematic investigation of Reduce and AllReduce on the Cerebras Wafer-Scale Engine…

This paper addresses the challenge of providing portable and highly efficient code structures for CPU and GPU architectures. We choose the assembly of the right-hand term in the incompressible flow module of the High-Performance…

Quantum field theories underlie all of our understanding of the fundamental forces of nature. The are relatively few first principles approaches to the study of quantum field theories [such as quantum chromodynamics (QCD) relevant to the…

Quantum Error Correction (QEC) is essential for future quantum computers due to its ability to exponentially suppress physical errors. The surface code is a leading error-correcting code candidate because of its local topological structure,…

The two innermost layers of the ALICE inner tracking system are instrumented with silicon pixel detectors. Single chip assembly prototypes of the ALICE pixels have been tested in high energy particle beams at the CERN SPS. Detection…

The use of analog classical systems for computation is generally thought to be a difficult proposition due to the susceptibility of these devices to noise and the lack of a clear framework for achieving fault-tolerance. We present…

Modern GPUs are able to perform significantly more arithmetic operations than transfers of a single word to or from global memory. Hence, many GPU kernels are limited by memory bandwidth and cannot exploit the arithmetic power of GPUs.…

A status report is given of the QCDOC project, a massively parallel computer optimized for lattice QCD using system-on-a-chip technology. We describe several of the hardware and software features unique to the QCDOC architecture and present…

There is a large body of legacy scientific code written in languages like Fortran that is not optimised to get the best performance out of heterogeneous acceleration devices like GPUs and FPGAs, and manually porting such code into parallel…

Superconducting coupler architecture demonstrates great potential for scalable and high-performance quantum processors, yet how to design efficiently and automatically 'Qubit-Coupler-Qubit (QCQ)' of high performance from the layout…

The design and implementation of Deep Learning (DL) models is currently receiving a lot of attention from both industrials and academics. However, the computational workload associated with DL is often out of reach for low-power embedded…

Interconnecting clusters of qubits will be an essential element of scaling up future quantum computers. Operations between quantum processing units (QPUs) are usually significantly slower and costlier than those within a single QPU, so…

Managing the high computational cost of iterative solvers for sparse linear systems is a known challenge in scientific computing. Moreover, scientific applications often face memory bandwidth constraints, making it critical to optimize data…

We describe the construction of a high performance parallel computer composed of PC components, as well as the performance test in lattice QCD.

The design of low-density parity-check (LDPC) code ensembles optimized for a finite number of decoder iterations is investigated. Our approach employs EXIT chart analysis and differential evolution to design such ensembles for the binary…

High-performance computing systems are more and more often based on accelerators. Computing applications targeting those systems often follow a host-driven approach in which hosts offload almost all compute-intensive sections of the code…

Clifford gates play a role in the optimisation of Clifford+T circuits. Reducing the count and the depth of Clifford gates, as well as the optimal scheduling of T gates, influence the hardware and the time costs of executing quantum…