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CPU simulators are vital for computer architecture research, primarily for estimating performance under different programs. This poses challenges for fast and accurate simulation of modern CPUs, especially in multi-core systems. Modern CPU…

Performance · Computer Science 2025-10-14 Buqing Xu , Jianfeng Zhu , Yichi Zhang , Qinyi Cai , Guanhua Li , Shaojun Wei , Leibo Liu

E769 has just recorded on tape the interactions of 500 million pions, kaons, and protons. A Cerenkov counter and a TRD were used to tag beam particle types in both positive and negative 250 GeV/c hadron beams. Thin foil Be, Al, Cu, and W…

High Energy Physics - Experiment · Physics 2007-05-23 D. J. Summers

The rapid growth of AI-based Internet-of-Things applications increased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As a consequence, vector processor architectures, traditionally…

Last level cache management and core interconnection network play important roles in performance and power consumption in multicore system. Large scale chip multicore uses mesh interconnect widely due to scalability and simplicity of the…

Distributed, Parallel, and Cluster Computing · Computer Science 2015-08-14 Navin Kumar , Aryabartta Sahu

Reservoir computing (RC) is a leading machine learning algorithm for information processing due to its rich expressiveness. A new RC paradigm has recently emerged, showcasing superior performance and delivering more interpretable results…

Emerging Technologies · Computer Science 2024-07-09 Dongliang Wang , Yikun Nie , Gaolei Hu , Hon Ki Tsang , Chaoran Huang

In this paper, we further develop a family of parallel time integrators known as Revisionist Integral Deferred Correction methods (RIDC) to allow for the semi-implicit solution of time dependent PDEs. Additionally, we show that our…

Distributed, Parallel, and Cluster Computing · Computer Science 2012-09-20 Benjamin Ong , Andrew Melfi , Andrew Christlieb

Scalable implementation of quantum networks and photonic processors require integrated photonic memories with high efficiency, yet current integrated systems have been limited to storage efficiencies below 27.8%. Here, we demonstrate highly…

All-pairs shortest paths (APSP) remains a major bottleneck for large-scale graph analytics, as data movement with cubic complexity overwhelms the bandwidth of conventional memory hierarchies. In this work, we propose RAPID-Graph to address…

Hardware Architecture · Computer Science 2026-01-29 Yanru Chen , Zheyu Li , Keming Fan , Runyang Tian , John Hsu , Weihong Xu , Minxuan Zhou , Tajana Rosing

We report the first end-to-end hardware-validated demonstration of a reversible Quantum Memory Matrix QMM imprint retrieval cycle. Using IBM Quantum back ends, we realize five imprint retrieval experiments that scale from a minimal…

General Physics · Physics 2025-06-12 Florian Neukart , Eike Marx , Valerii Vinokur

Modern GPU systems are constantly evolving to meet the needs of computing-intensive applications in scientific and machine learning domains. However, there is typically a gap between the hardware capacity and the achievable application…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-10-02 Gabin Schieffer , Ruimin Shi , Stefano Markidis , Andreas Herten , Jennifer Faj , Ivy Peng

Retrieval-Augmented Generation (RAG) enhances large language models (LLMs) by integrating external knowledge retrieval but faces challenges on edge devices due to high storage, energy, and latency demands. Computing-in-Memory (CIM) offers a…

The Artificial Intelligence models pose serious challenges in intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters. Silicon photonic technologies, owing to their high speed, low…

Many recent papers have demonstrated fast in-network computation using programmable switches, running many orders of magnitude faster than CPUs. The main limitation of writing software for switches is the constrained programming model and…

Networking and Internet Architecture · Computer Science 2022-12-14 Stephen Ibanez , Alex Mallery , Serhat Arslan , Theo Jepsen , Muhammad Shahbaz , Changhoon Kim , Nick McKeown

PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology, for photomultipliers array. It is a front-end electronics ASIC which allows triggerless acquisition for the next generation of neutrino experiments. These detectors…

Instrumentation and Detectors · Physics 2014-11-20 G. Martin-Chassard , S. Conforti Di Lorenzo , F. Dulucq , M. El Berni , C. de La Taille , W. Wei

The demand for energy-efficient and high performance embedded systems drives the evolution of new hardware architectures, including concepts like approximate computing. This paper presents a novel reconfigurable embedded platform named…

Hardware Architecture · Computer Science 2024-10-02 Arvin Delavari , Faraz Ghoreishy , Hadi Shahriar Shahhoseini , Sattar Mirzakuchaki

Deep learning-based recommendation models (DLRMs) are widely deployed in commercial applications to enhance user experience. However, the large and sparse embedding layers in these models impose substantial memory bandwidth bottlenecks due…

Hardware Architecture · Computer Science 2025-09-16 Yu-Hong Lai , Chieh-Lin Tsai , Wen Sheng Lim , Han-Wen Hu , Tei-Wei Kuo , Yuan-Hao Chang

This work discusses the implementation of Markov Chain Monte Carlo (MCMC) sampling from an arbitrary Gaussian mixture model (GMM) within SRAM. We show a novel architecture of SRAM by embedding it with random number generators (RNGs),…

Signal Processing · Electrical Eng. & Systems 2020-03-06 Priyesh Shukla , Ahish Shylendra , Theja Tulabandhula , Amit Ranjan Trivedi

Real-time data processing is a central aspect of particle physics experiments with high requirements on computing resources. The LHCb experiment must cope with the 30 million proton-proton bunches collision per second rate of the Large…

Nowadays, as the ever-increasing demand for more powerful computing resources continues, alternative advanced computing paradigms are under extensive investigation. Significant effort has been made to deviate from conventional Von Neumann…

Neural and Evolutionary Computing · Computer Science 2024-10-10 Bernard J. Giron Castro , Christophe Peucheret , Darko Zibar , Francesco Da Ros

One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support…

Hardware Architecture · Computer Science 2011-11-09 I. Papaefstathiou , T. Orphanoudakis , G. Kornaros , C. Kachris , I. Mavroidis , A. Nikologiannis