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Sub-picosecond timing synchronization can enable future optical timekeeping networks, including coherent phased array radar imaging at GHz levels, intercontinental clock comparisons for the redefinition of the second, chronometric leveling,…

Logic locking has become a promising approach to provide hardware security in the face of a possibly insecure fabrication supply chain. While many techniques have focused on locking combinational logic (CL), an alternative latch-locking…

We present a scalable, clockless up-down counter architecture implemented using single-flux quantum (SFQ) logic to enable efficient state management in superconductor digital systems. The proposed design eliminates the reliance on clocked…

We present a latch-based and PLL-free design of the voltage droop correction circuit of Lenzen, Fuegger, Kinali, and Wiederhake\cite{DroopJournal}. Such a circuit dynamically modifies the clock frequency of a digital clock for VLSI systems.…

One of the prevailing challenges in Computational Fluid Dynamics is accurate simulation of two-phase flows involving heat and mass transfer across the fluid interface. This is currently an active field of research, which is to some extend…

Obtaining flow-level measurements, similar to those provided by Netflow/IPFIX, with OpenFlow is challenging as it requires the installation of an entry per flow in the flow tables. This approach does not scale well with the number of…

Two-phase outflows refer to situations where the interface formed between two immiscible incompressible fluids passes through open portions of the domain boundary. We present in this paper several new forms of open boundary conditions for…

Level-sensitive latches are widely used in high- performance designs. For such circuits efficient statistical timing analysis algorithms are needed to take increasing process vari- ations into account. But existing methods solving this…

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the…

We propose a variant of the $\theta$-scheme for diffuse interface models for two-phase flow, together with three new linearization techniques for the surface tension. These involve either additional stabilizing force terms, or a fully…

In the traditional Application-Specific Integrated Circuit (ASIC) design flow, the concept of timing closure implies to reach convergence during physical synthesis such that, under a given area and power budget, the design works at the…

Even though it seems that FPGAs have finally made the transition from research labs to the consumer devices' market, programming them remains challenging. Despite the improvements made by High-Level Synthesis (HLS), which removed the…

Multivariate time-series (MTS) forecasting is fundamental to applications ranging from urban mobility and resource management to climate modeling. While recent generative models based on denoising diffusion have advanced state-of-the-art…

Orthogonal time frequency space (OTFS) is a 2-dimensional (2D) modulation technique designed in the delay-Doppler domain. A key premise behind OTFS is the transformation of a time varying multipath channel into an almost non-fading 2D…

The new vision presented is aimed to overcome the logic overhead issues that previous works exhibit when applying GALS techniques to programmable logic devices. The proposed new view relies in a 2-phase, bundled data parity based protocol…

We show how a recently published 2d model for traffic flow can be further improved. Besides other improvements and simplifications, we present not only a method to compute the necessary time step restrictions, but also a subcycling for the…

Future optical clock networks will require free-space optical time-frequency transfer between flying clocks. However, simple one-way or standard two-way time transfer between flying clocks will completely break down because of the…

In safety-critical autonomous systems, data freshness presents a fundamental design challenge. While the Logical Execution Time (LET) paradigm ensures compositional determinism, it often does so at the cost of injected latency, degrading…

As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest, several works have hacked existing backend tools to explore…

In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…